Program

Following is the program schedule for the 8th International Symposium on Networks-on-Chip (NOCS-14).

(PDF of the program schedule can be downloaded here.)


NOCS14

8th IEEE/ACM International Symposium on Networks-on-Chip
September 17th - 19th, 2014
Ferrara, Italia



Wednesday, September 17th, 2014

8.00 - 8.45 REGISTRATION
8.45 - 9.00 OPENING AND WELCOME
9.00 - 10.00 KEYNOTE ADDRESS
High-Performance Energy-Efficient NoC Fabrics: Evolution and Future Challenges
Mark A. Anders, Circuit Research Lab - Intel (USA).
SLIDES
10.00 - 11.00 PAPER SESSION 1: NoC ARCHITECTURE I
Session Chair: Federico Angiolini (iNoCs)
  1. Single-Cycle Collective Communication Over A Shared Network Fabric
    Tushar Krishna, Li-Shiuan Peh.
    MIT
  2. SLIDES

  3. Extending Bufferless On-Chip Networks to High-Throughput Workloads
    Hanjoon Kim, Changhyun Kim, Miri Kim, Kanghee Won, John Kim.
    KAIST
11.00 - 11.30 COFFEE BREAK
11.30 - 13.00 PAPER SESSION 2: NoC ARCHITECTURE II
Session Chair: Natalie Enright Jerger (University of Toronto)
  1. An Efficient Network-on-Chip (NoC) Based Multicore Platform for Hierarchical Parallel Genetic Algorithms
    Yuankun Xue1, Zhiliang Qian2, Guopeng Wei3, Paul Bogdan4, Chi-Ying Tsui2, Radu Marculescu3.
    1Fudan University, 2The Hong Kong University of Science and Technology, 3Carnegie Mellon University,
    4University of Southern California
  2. SLIDES

  3. Achieving Balanced Buffer Utilization with a Proper Co-Design of Flow Control and Routing Algorithm
    Dong Xiang1, Miguel Gorgues Alonso2, José Flich2, José Duato2.
    1Tsinghua University, 2Universidad Politécnica de Valencia
  4. SLIDES

  5. FMEA-Based Analysis of a Network-on-Chip for Mixed-Critical Systems
    Eberle A. Rambo, Alexander Tschiene, Jonas Diemer, Leonie Ahrendts, Rolf Ernst.
    Technische Universität Braunschweig
  6. SLIDES
13.00 - 14.30 LUNCH
14.30 - 16.00 EMBEDDED TUTORIAL
OpenSoC: a Flexible, Parameterizable, Open NoC Generation Tool
Organizers:
Farzad Fatollahi-Fard, Lawrence Berkeley National Laboratory,
David Donofrio, Lawrence Berkeley National Laboratory,
George Michelogiannakis, Lawrence Berkeley National Laboratory.
SLIDES
16.00 - 16.30 COFFEE BREAK
16.30 - 18.30 PAPER SESSION 3: MODELING AND ANALYSIS
Session Chair: José Flich (Universidad Politecnica de Valencia)
  1. Sampling-Based Approaches to Accelerate Network-on-Chip Simulation
    Wenbo Dai, Natalie Enright Jerger.
    University of Toronto
    SLIDES

  2. An Analytical Model for Worst-case Reorder Buffer Size of Multi-path Minimal Routing in NoCs
    Gaoming Du1, Miao Li1, Zhonghai Lu2, Minglun Gao1, Chunhua Wang3.
    1Institute of VLSI Design, Hefei University of Technology, 2KTH Royal Institute of Technology,
    3School of Microelectronics, Hefei University of Technology
  3. SLIDES

  4. Transient Queuing Models for Input-Buffered Routers in Network-on-Chip
    David Oehmann, Erik Fischer, Gerhard Fettweis.
    Technische Universität Dresden

  5. Towards Stochastic Delay Bound Analysis for Network-on-Chip
    Zhonghai Lu1, Yuan Yao1, Yuming Jiang2.
    1KTH Royal Institute of Technology, 2Norwegian University of Science and Technology (NTNU)
  6. SLIDES
18.30 CLOSING


Thursday, September 18th, 2014

EMERGING TECHNOLOGY MORNING
8.30 - 9.45 SPECIAL SESSION 1
SILICON PHOTONIC INTERCONNECTS: AN ILLUSION OR A REALISTIC SOLUTION?
Organizers:
Jiang Xu - Hong Kong University of Science and Technology
Sébastien Le Beux - Lyon Institute of Nanotechnology
Yvain Thonnart - CEA LETI
  1. Technology Assessment of Silicon Interposers for Manycore SoCs: Active, Passive, or Optical?
    Yvain Thonnart.
    CEA-Leti, France
    SLIDES

  2. Towards Compelling Cases for the Viability of Silicon-Nanophotonic Technology in Future Manycore Systems
    Luca Ramini1, Hervè Tatenguem Fankem1 , Alberto Ghiribaldi1, Paolo Grani2, Marta Ortìn Obòn3, Anja Boos4, Sandro Bartolini2.
    1University of Ferrara, 2University of Siena,3University of Zaragoza, 4TU Munich
  3. SLIDES

  4. CLAP: a Crosstalk and Loss Analysis Platform for Optical Interconnects
    Mahdi Nikdast1, Luan H. K. Duong1, Jiang Xu1, Sébastien Le Beux2, Xiaowen Wu1, Zhehui Wang1, Peng Yang1, and Yaoyao Ye1.
    1Hong Kong University of Science and Technology, 2Lyon Institute of Nanotechnology
  5. SLIDES
9.45 - 11.00 SPECIAL SESSION 2
INTERCONNECT ENHANCES ARCHITECTURE: EVOLUTION OF WIRELESS NoC FROM PLANAR TO 3D
Organizers:
Radu Marculescu - Carnegie Mellon University
Partha Pratim Pande - Washington State University
Deukhyoun Heo - Washington State University
Hiroki Matsutani - Keio University
  1. Foundations of On-chip Communication: Performance and Power Management in 2D and 3D Multicore Platforms
    Radu Marculescu.
    Carnegie Mellon University
    SLIDES

  2. Planar Wireless NoC Architectures
    Partha Pratim Pande, Deukhyoun Heo.
    Washington State University
    SLIDES

  3. 3D Wireless NoC Architectures
    Hiroki Matsutani.
    Keio University
  4. SLIDES
11.00 - 11.30 COFFEE BREAK
11.30 - 13.00 PAPER SESSION 4: OPTICAL NoCs
Session Chair: Sandro Bartolini (University of Siena)
  1. Augmenting Manycore Programmable Accelerators with Photonic Interconnect Technology for the High-End Embedded Computing Domain
    Marco Balboni1, Marta Ortín Obón2, Alessandro Capotondi3, Alberto Ghiribaldi1, Herve Tatenguem Fankem1, Luca Ramini1, Víctor Viñals2, Andrea Marongiu4, Davide Bertozzi1.
    1University of Ferrara, 2University of Zaragoza, 3University of Bologna, 4ETH Zurich
    SLIDES

  2. QuT: A Low-Power Optical Network-on-Chip
    Parisa Khadem Hamedani1, Natalie Enright Jerger1, Shaahin Hessabi2.
    1University of Toronto, 2Sharif University of Technology
  3. SLIDES

  4. Sharing and Placement of On-chip Laser Sources in Silicon-Photonic NoCs
    Chao Chen, Tiansheng Zhang, Pietro Contu, Jonathan Klamkin, Ayse Coskun, Ajay Joshi.
    Boston University
  5. SLIDES
13.00 - 14.30 LUNCH
14.30 - 16.30 PAPER SESSION 5: LOW POWER NoCs
Session Chair: Giorgos Dimitrakopoulos (Democritus University of Thrace)
  1. Variable-Width Datapath for On-Chip Network Static Power Reduction
    George Michelogiannakis, John Shalf.
    Lawrence Berkeley National Laboratory
  2. SLIDES

  3. Dynamic Synchronizer Flip-Flop Performance in FinFET Technologies
    Mark Buckler1, Arpan Vaidya2, Xiaobin Liu2, Wayne Burleson3.
    1University of Massachusetts Amherst, 2 University of Massachusetts Amherst,3 AMD Research
    SLIDES

  4. Design of a Low Power NoC Router using Marching Memory Through type
    Ryota Yasudo1, Takahiro Kagami1, Hideharu Amano1, Yasunobu Nakase2, Masashi Watanabe2, Tsukasa Oishi2, Toru Shimizu2, Tadao Nakamura1 .
    1Keio University, 2Renesas Electronics Corp.
  5. SLIDES

  6. Bubble Sharing: Area and Energy Efficient Adaptive Routers using Centralized Buffers
    Syed Minhaj Hassan, Sudhakar Yalamanchili.
    Georgia Institute of Technology
  7. SLIDES
16.30 - 18.00 COFFEE BREAK AND POSTER SESSION

STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip
Shalimar Rasheed, Paul Gratz, Srinivas Shakkottai, Jiang Hu
Texas A&M University

Hermes: Architecting a Top-Performing Fault-Tolerant Routing Algorithm for Networks-on-Chips
Vassos Soteriou1, Costas Iordanou1, Konstantinos Aisopos2, Elena Kakoulli1
1Cyprus University of Technology, 2Microsoft Corporation, USA

Scalability-Oriented Multicast Traffic Characterization
Sergi Abadal1, Raúl Martínez2, Eduard Alarcón1, Albert Cabellos-Aparicio1
1N3Cat at Universitat Politécnica de Catalunya (UPC), 2Intel Labs Barcelona

An OFDMA Based RF Interconnect for Massive Multi-core Processors
Eren Unlu1, Christophe Moy1, Mohamad Hamieh2, Myriam Ariaudo2, Yves Louet1, Emmanuelle Bourdel2, Frédéric Drillet2, Alexandre Briere3, Julien Denoulet3, Andrea Pinna3, Lounis Zerioul2, Bertrand Granado3, Patrick Garda3, François Pêcheux3, Cédric Duperrier2, Sébastien Quintanel2, Olivier Romain2
1Supelec-IETR, 2ENSEA, 3LIP6

CHARM: A Low-Cost Congestion-Aware and Highly Adaptive Routing Method for 2D and 3D On Chip Networks
Manoj Kumar1, Manoj Singh Gaur1, Vijay Laxmi1, Masoud Daneshtalab2, Pankaj Kumar1, Seok-Bum Ko3, Mark Zwolinski4
1Malaviya National Institute of Technology, Jaipur, 2University of Turku, 3University of Saskatchewan, 4University of Southampton

Design Trade-offs in Energy Efficient NoC Architectures
Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios Pnevmatikatos
FORTH-ICS

Effective Abstraction for Response Proof of Communication Fabrics
Sayak Ray, Sharad Malik
Princeton University

DyAFNoC: Characterization and Analysis of a Dynamically Reconfigurable NoC using a DOR-based Deadlock-Free Routing Algorithm
Ernesto Cristopher Villegas Castillo, Gabriele Miorandi, Wang Jiang Chau
University of Sao Paulo

An Energy-Efficient Millimeter-Wave Wireless NoC with Congestion-Aware Routing and DVFS
Ryan Kim, Jacob Murray, Paul Wettin, Partha Pande, Behrooz Shirazi.
Washington State University

18.00 CLOSING
19.30 SOCIAL EVENT AT THE MEDIEVAL CASTLE OF FERRARA


Friday, September 19th, 2014

9.00 - 10.00 KEYNOTE ADDRESS
SpinNNaker: the World's Biggest NoC
Steve Furber - University of Manchester (UK)
SLIDES
10.00 - 11.00 PAPER SESSION 6: FAULT TOLERANCE AND RELIABILITY
Session Chair: Partha Pande (Washington State University)
  1. DiAMOND: Distributed Alteration of Messages for On-Chip Network Debug
    Rawan Abdel-Khalek, Valeria Bertacco.
    University of Michigan
  2. SLIDES

  3. ElastiNoC: A Self-Testable Distributed VC-based Network-on-Chip Architecture
    Ioannis Seitanidis1, Anastasios Psarras1, Emmanouil Kalligeros2, Chrysostomos Nicopoulos3, Giorgos Dimitrakopoulos1.
    1Democritus University of Thrace, 2University of the Aegean, 3University of Cyprus
  4. SLIDES
11.00 - 13.00 PAPER SESSION 7: NoC ARCHITECTURE III
Session Chair: Igor Loi (University of Bologna)

  1. A Loosely Synchronizing Asynchronous Router for TDM-Scheduled NOCs
    Ioannis Kotleas1, Dean Humphreys1, Rasmus Bo Sørensen1, Evangelia Kasapaki1, Florian Brandner2, Jens Sparsø1
    1Technical University of Denmark, 2ENSTA ParisTech, France
  2. SLIDES

  3. ICARO: Congestion Isolation in Networks-On-Chip
    Jose Vicente Escamilla Lopez1, José Flich1, Pedro Javier Garcia2
    1Universitat Politécnica de Valéncia, 2Universidad de Castilla-La Mancha
  4. SLIDES

  5. Using Packet Information for Efficient Communication in NoCs
    Prasanna Venkatesh Rengasamy, Madhu Mutyam.
    IIT Madras
  6. SLIDES
13.00 - 13.30 BEST PAPER AWARD AND CLOSING
13.30 LUNCH