High-Performance Energy-Efficient NoC Fabrics: Evolution and Future Challenges
ABSTRACT
As exa-scale microprocessor and SoC core and IP block counts increase, networks-on-chip are increasingly becoming performance and power limiters. Recent scaling and integration trends pose further challenges for on-die communication networks with topologies that have evolved from crossbars to rings to 2D meshes. These future challenges include i) reducing energy associated with global clock distribution, synchronization, and data storage, ii) adapting to process, voltage, and temperature variations, and iii) flexibility for different operating voltages, frequencies, and IP blocks. In this presentation, we will review some of the key network-on-chip scaling trends and challenges as well as discuss architecture and circuit solutions. Recent advancements implemented in 22nm tri-gate CMOS to demonstrate the combination of hybrid packet/circuit switching with source-synchronous operation to address these challenges by removing intra-route data storage and costly global clock distribution power will be presented.