Our Research Mission

Interconnection networks are the central component of modern computer systems across a wide range of system scales. They connect processors with one another, with memories and with I/O devices both in supercomputers and on-chip; they provide the fabric for network switches and routers in data centers, and they are the system integration framework for systems-on-chip. Historically, they have been key enablers for fast messaging, scalable processing and memory architectures in parallel computing machines, or for flexible and cost-effective system integration in embedded computing platforms. Today, a key structural change overtaking computing is the move towards a low-power computing continuum spanning embedded systems, mobile devices, microservers, high-performance computing machines and data centers. Again, the success of this trend depends on the capability to bring interconnection networks into new ground. In the embedded computing domain, emerging heterogeneous parallel computing architectures require a hierarchy of interconnection fabrics, providing efficient support for complex workloads such as multi-programmed and mixed-criticality ones. At the opposite side of the computing spectrum, architectures inspired by the same concepts (parallelism, heterogeneity) are running the race to exascale computing at full speed, but only interconnection networks with disruptive features in terms of bandwidth, energy-per-bit and seamless scalability can make them hit the target. The mission of this research group is to stay at the forefront of system innovation at different scales (embedded systems, microservers, high-performance computing) by leveraging the enabling features of communication architectures and technologies.








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If you are interested in joining our research group, we offer numerous undergraduate, graduate, and post-graduate research opportunities.

PeopleAvailable Theses

Group Spotlight

Industrial Validation of our asynchronos network-on-chip.

Following a collaboration between Columbia University (USA), AMD Research (USA), Univ. of Massachusetts Amherst (USA) and University of Ferrara, the two-phase bundled-data network-on-chip switch designed in Ferrara has been successfully validated in an industrial environment at AMD Research. The outcome will be presented at the industrial track of ACM/IEEE DATE-17 in Lausanne on March 29th. The implementation was made on an advanced 14nm FinFET technology.

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Research Areas



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Spatial-Division Multiplexing of Many-Core Systems

  • Software parallelism does not keep up with hardware parallelism.
  • New sharing models are needed for massively parallel somputing systems
  • Our approach: cross-layer support for partitioning and isolation

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Adaptive Partitioning and Isolation

  • Resource management for multi-programmed workloads is a challenge
  • Goal: reduce energy-to-solutions
  • We envision dynamic harware architectures



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Hardware-Assisted Embedded System Virtualization

  • Virtualization as a means of simplifying programming
  • Hypervisor-level resource management
  • Dynamic hardware to compose application requirements together


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Asynchronous Interconnect Technology for GALS Systems

  • Globally-Asynchronous Locally-Synchronous (GALS) design for low-power
  • Striving to preserve a clock or going clock-less?
  • Our approach: transition-signaling bundled-data NoC architectures


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Photonic integration of Microservers

  • Microservers target orders of magnitude reduction in power
  • Efficient orchestration of computation nodes is key for performance
  • Current Interconnection networks enable only a spatially-limited notion of locality

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Design Automation Beyond its Electronic Roots

  • Success of emerging nanotechnologies: not just technology maturity
  • Novel synthesis methods needed to unfold logic expressivity
  • Logic synthesis as technology enabler


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The CAD Challenge for the Design of Future Interconnection Networks

  • Full-custom design is not an option anymore
  • Need to bridge the gap between system designers and technology developers
  • Both evolutionary and revolutionary interconnect solutions need for design automation for industrial uptake

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Feature-rich Communication Architectures with Emerging Technologies and Interfaces

  • Once upon a time, NoCs were all about buffering, switching, allocation and flow-control
  • Today they are much more: fault-tolerance, testing, reconfiguration, notifications,etc.
  • Relatively simple in electronics, but with photonics...

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Going off-Chip: Optical Interconnection Networks for High-Performance Computing

  • Exascale-computing calls for disruptive data-movement solutions
  • New class of real-time big-data applications are latency-critical
  • Our focus: optical networking for low-latency and performace-predictability

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Latest Publications

Here is the list of latest publications from the MPSoC Research Group.


  • Marta Ortın-Obon, Mahdi Tala, Luca Ramini, Vıctor Vinals-Yufera, Davide Bertozzi,"Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies subject to the Floorplanning, Placement and Routing Constraints of a 3D-Stacked System", TVLSI 2017

  • Marco Balboni and Davide Bertozzi,"Making the Case for Space-Division Multiplexing of Programmable Many-Core Accelerators", Design, Automation and Test in Europe (DATE), 2017

  • University of Ferrara, AMD Research, Columbia University, University of Massachusets Amherst,"An Asynchronous NoC Router in a 14nm FinFET Library: Comparison to an Industrial Synchronous Counterpart", Design, Automation and Test in Europe (DATE), 2017

  • Marco Balboni and Davide Bertozzi,"Transparent Lifetime Built-In Self-Testing of Networks-on-Chip Through the Selective Non-Concurrent Testing of their Communication Channels", 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS), 2017

  • Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann "PROTON+: A Placement and Routing Tool for 3D Optical Networks-on- Chip with a Single Optical Layer.", JETC 12(4), 2016

  • Mahdi Tala, Marco Castellari, Marco Balboni and Davide Bertozzi "Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive", Networks-on-Chip (NOCS), 2016 Tenth IEEE/ACM International Symposium on, 1--8, IEEE, 2016

  • Gabriele Miorandi, Alberto Celin, Michele Favalli and Davide Bertozzi "A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations", Networks-on-Chip (NOCS), 2016 Tenth IEEE/ACM International Symposium on, 1--8, IEEE, 2016

  • Gabriele Miorandi, Mahdi Tala, Marco Balboni, Luca Ramini and Davide Bertozzi "Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems", Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, ACM, 2016

  • Marco Balboni and Davide Bertozzi "NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators", Proceedings of International Conference on High Performance Computing & Simulation (HPCS), pp.643-645. 2015

  • Marco Balboni, José Flich and Davide Bertozzi "Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration.", Proceedings of DATE, pp.806-811. 2015

  • Marta Ortin Obon, Luca Ramini, Marco Balboni, Maddalena Nonato, Victor Vinals and Davide Bertozzi "Partitioning Strategies of Wavelength-Routed Optical Networks-on- Chip for Laser Power Minimization.", Workshop on Exploiting Silicon Photonics for Energy-Efficient High-Performance Computing (SiPhotonics), page 17--24, DOI: 10.1109/SiPhotonics, 2015

  • Luca Ramini and Davide Bertozzi, "Design Space Exploration of Wavelength-Routed Optical Networks-on-Chip Topologies for 3D Stacked Multi-and Many-Core Processors", VLSI: Circuits for Emerging Applications, CRC Press, 147--178, 2015

  • Davide Bertozzi, Stefano di Carlo, Salvatore Galfano, Marco Indaco, Piero Olivo, Paolo Prinetto, Cristian Zambelli, "Performance and reliability analysis of cross-layer optimizations of NAND flash controllers", ACM Transactions on Embedded Computing Systems (TECS), vol. 14, ACM, 2015

  • Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag "The fast evolving landscape of on-chip communication.", Selected future challenges and research avenues. Design Autom. for Emb. Sys. 19(1-2): 59-76, 2015



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Visitors Information

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MPSoC Research Group Location

Università degli Studi di Ferrara
ENDIF, ENgineering Department In Ferrara
Building "Blocco A"
via Saragat 1
Ferrara (FE), 44122
ITALY
Phone: (+39) 0532 974832
              (+39) 0532 974989

The laboratory is located on the third floor (the Blue Floor) of the Engineering Department, room 319, 305 and 306. The building has a ground-level entrance, where an elevator or a staircase lead up to the third floor.







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