7th International Workshop on
Interconnection Network Architecture:
On-Chip, Multi-Chip (INA-OCMC)

The Workshop

INA-OCMC is a network oriented workshop presenting original work in the field of on-chip, multi-chip interconnection network architecture. The workshop aims at bringing together researchers and engineers from industry and academia to share ideas and thoughts about networking of devices in both the off-chip and the on-chip environment, each with its own design constraints. This is the seventh edition of the workshop. In the previous editions the workshop exhibited a competent audience and interesting discussions arose from the different presentations of authors and from the keynote, thus promoting joint research initiatives.

Organizing Committee

General Chairs

• Davide Bertozzi, University of Ferrara, Italy

• Cyriel Minkenberg, IBM Zurich Research Lab, Switzerland

Program Chairs

• Sören Sonntag, Intel, Germany

• Giorgos Dimitrakopoulos, Democritus University of Thrace, Greece

Steering Committee

• José Duato, Technical University of Valencia, Spain

• Manolis Katevenis, FORTH, Greece

Publicity Chair

• Frank Olaf Sem-jacobsen, Simula, Norway

Publication Chair

• Alberto Ghiribaldi, University of Ferrara, Italy

Special Session Chair

• José Flich, Technical University of Valencia, Spain

Technical Scope

When interconnecting different end-nodes in on-chip and multi-chip processing architectures, the communication infrastructure plays a dominant role in determining overall system metrics such as performance, reliability and often even area and power. On the other hand, each application domain poses its own design constraints that the interconnect fabric has to cope with, thus leading to well differentiated architecture design principles. Ultimately, careful engineering of the interconnection network is at the core of the successful development of both on-chip and multi-chip processing architectures.

The program of the workshop is organized around two main directions. The first direction includes original papers describing new and previously unpublished results on all aspects of interconnection network architectures. Topics of interest include but are not limited to:

• Networks-on-Chip (NoC)

• Multi-Chip Interconnection Networks, including Cluster Interconnects

• "Commodity Switches" as general-purpose building blocks

• Switching, buffering, and routing architectures

• Flow control and congestion management in switching fabrics

• Virtualization

• Topology exploration

• Timing, synchronous/asynchronous communication

• Reliability, availability, fault tolerance

• Area/power versus functionality/QoS support in NoC architectures

• NoC physical link design

• NoC testing and verification

• Programming models for NoC-centric systems