Internship opportunities for master theses available at: IHP Microelectronics (Germany), Technical University of Munich (Germany), Universidad Politecnica de Valencia (Spain), Universidad Catolica de Murcia (Spain), Alstom Ferroviaria Spa (Bologna, Italy), EdaLab s.r.l (Verona, Italy), Camlin Ltd (Parma, Italy). Other destinations are available on demand.

Welcome to the 2019/2020 course on
Embedded System Architectures.

Course Schedule


The Focus of the Course

The main learning objective is to provide basic notions on the architectures and on the synthesis methodologies (both front-end and back-end) of systems-on-chip for the embedded computing domain. Acquired knowledge will include:
- Knowledge of the front-end synthesis steps based on the principle of the progressive refinement of the abstraction layer. To this end, knowledge of the SystemC modeling and simulation language.
- Knowledge of the back-end synthesis steps, changing a technology-independent specification into a mapped gate-level implementation based on a generic technology library. To this end, knowledge of the semi-custom design methodology based on standard cells.
- Knowledge of the "HOST CPU" performing control tasks in modern heterogeneous parallel computing architectures. Knowledge will include CPU microarchitectures and optimization techniques for performance.
- Basic knowledge of the "Single Instruction Multiple Data" processing and of GPU architectures.
- Knowledge of the memory hierarchy and of its management techniques, both in hardware and in software.
- Basic knowledge of the different acceleration methods of computation kernels, both through hardwired accelerators and through reconfigurable logic.
- Knowledge of protocols, topologies and architectures for on-chip communication, in order to implement the global system integration framework.



The exam is split into two parts:
- Achievement of a "pass" evaluation for Lab activities.
- Oral Exam.

  • A) Pass/Fail evaluation of Lab activities.
    Lab activities are structured as a predefined sequence of guided Lab experiences. For each of them, students have to get a "pass" evaluation that certifies the progressive and solid increments of his maturity in hardware modeling and simulation. Once a "pass" is obtained in each Lab exercise, the student is entitled to pass the exam.

  • B) Oral exam.
    In the oral exam the student's ability to expose topics in an appropriate and rigorous way will be tested. At the same time, the oral exam intends to test his ability to establish logical links between affine topics covered during the course. The oral exam consists of three questions, that tentatively cover most of the topics addressed by the instructor during the lectures.

    The two parts of the exam are not subject to temporal constraints: the pass/fail evaluation can be obtained before or after the oral exam. A "pass" in the Lab exercises entitles the student to pass the exam (i.e., to confirm the mark of the oral exam, regardless it has been already passed or not); it is not a requirement to be admitted to the oral exam. The final mark is thus the mark of the oral exam only.

One third of the course will be devoted to the fundamentals of SystemC programming through lab experiences.


Course Program

  • Introduction to Embedded Computing, and its positioning in the context of global computing framework.

  • Architectural template of a System-on-Chip (SoC).

  • Virtual prototyping through SystemC.

  • SystemC syntax and Lab exercises.

  • Host CPU: recalling pipelines, hazard detection units, forwarding units.

  • Host CPU: branch prediction techniques: static and dynamic ones.

  • Host CPU: architectures with multiple "execution paths" and reorder buffer.

  • Host CPU: architectures with out-of-order scheduling.

  • Host CPU: superscalar architectures.

  • Host CPU: VLIW architectures.

  • Host CPU and programmable accelerators: multi-core and many-core architectures.

  • GPUs: Single-Instruction Multiple-Data processing and architectures.

  • Accelerator Design: basics of standard cell design methodologies, hard macros and soft macros.

  • Reconfigurable Logic: basics of FPGA architectures.

  • Memory hierarchy.

  • Virtual memory.

  • Cache coherence protocols: snooping, directory-based.

  • Protocols and topologies for on-chip communication in low-end systems: AMBA AHB, AMBA AXI.

  • On-chip interconnection networks: topologies, routing, flow control, switching and architectures.


Course Material

  • Course Outline PDF

  • Lecture Ia: Overview of Computing Domains PDF

  • Lecture Ib: Embedded Systems Characteristics and Hardware Architecture PDF

  • Lecture Ic: Embedded Software Architecture and Emerging Trends PDF


    Lab Material



  • C++ basics PDF



  • Seminars from Camlin Group, Alstom Ferroviaria Italia, EdaLab srl and likely from Apple will be announced soon.


    2016 | This template has been adapted and modified by Marco Balboni.